High frequency clock synthesis is typically achieved by using a phase locked loop (PLL) to multiply up a reference clock signal to a frequency which is an integer multiple of the reference frequency. This is done by placing a divide-by-N element in the feedback path of the PLL, N being the desired multiplication factor. To accomplish noninteger multiplication of the reference clock frequency, a divide-by-M element can be placed at the input to the phase comparator, dividing the reference clock by M. In this manner, frequency multiplication by a factor N/M may be accomplished.
Prior art clock synthesizers typically use a voltage controlled oscillator (VCO) to synthesize the clock. A phase comparator compares the phase and frequency of the divided down synthesized clock to the reference clock, filters the phase/frequency error, and uses this signal to adjust the VCO frequency. This is done until the divided VCO clock is equal in frequency and phase to the reference clock. At this point, the VCO clock frequency itself is equal to exactly N times the reference clock frequency and is in phase with it.
A figure of merit of a clock generator is the amount of jitter on the synthesized clock signal. Noise sources on an integrated circuit die can cause the delay through the VCO stages to vary as the noise changes the instantaneous voltage across the delay stage. Differential delay stages can reduce this problem, but do not completely remove this source of jitter. Since a VCO is a closed loop of delay stages, the jitter accumulated through all of the VCO stages is used as an input of the VCO. This causes a further accumulation of the jitter and has been shown to increase the clock jitter by a factor of 10 to 100 above that of a clock edge propagating through an open delay chain. For example, if the edge jitter observed on the output of an open delay line is equal to lops (pico-seconds), then, if the delay line is closed (forming a VCO), the delay would increase by a factor of 10 to 100. The accumulation factor decreases as the bandwidth of the loop increases. A side effect of this jitter accumulation is low frequency jitter in the VCO, which causes the synthesized clock signal to be frequency modulated by a low frequency sine wave of frequency close to the PLL bandwidth.
Another source of jitter in the synthesized clock signal is the jitter introduced by the reference clock signal itself. Even with a perfect reference clock, the PLL uses a buffered version of this clock, where the delay through the buffer can be modulated by substrate noise.
These two sources of jitter, VCO noise and reference clock noise, result in a competing tradeoff between low and high loop bandwidth. A narrow band PLL will filter out the reference clock noise, but will give a higher jitter accumulation factor in the VCO. A wide band PLL will reduce jitter accumulation, but will permit more reference clock noise to be added to the clock jitter. Another side effect of very wide loop bandwidth is a loop transfer function with a badly underdamped response. In practical terms, the jitter accumulation factor will be a minimum of around 10.
Another problem with VCO based clock synthesizers is that the VCO jitter accumulation factor is proportional to the multiplication factor. This is because a divide by N in the feedback path implies that the VCO only gets corrected every N VCO cycles. This has the effect of narrowing PLL bandwidth.
What is desired is a circuit for synthesizing a clock signal having a frequency which is a multiple of a reference clock frequency and which does not suffer from the jitter and noise problems of existing VCO based circuits.